Microelectronic devices generally have a die (i.e., a chip) that includes integrated circuitry having a high density of very small components. In a typical process, a large number of dies are manufactured on a single wafer using many different processes that may be repeated at various stages (e.g., implanting, doping, photolithography, chemical vapor deposition, plasma vapor deposition, plating, planarizing, etching, etc.). The dies typically include an array of very small bond-pads electrically coupled to the integrated circuitry. The bond-pads are the external electrical contacts on the die through which the supply voltage, signals, etc., are transmitted to and from the integrated circuitry. The dies are then separated from one another (i.e., singulated) by dicing the wafer and backgrinding the individual dies. After the dies have been singulated, they are typically “packaged” to couple the bond-pads to a larger array of electrical terminals that can be more easily coupled to the various power supply lines, signal lines, and ground lines.
One type of microelectronic device is a “flip-chip” semiconductor device. These devices are referred to as “flip-chips” because they are typically manufactured on a wafer and have an active side with bond-pads that initially face upward. After manufacture is completed and a die is singulated, the die is inverted or “flipped” such that the active side bearing the bond-pads faces downward for attachment to a substrate. The bond-pads are usually coupled to terminals, such as conductive “bumps,” that electrically and mechanically connect the die to the substrate. The bumps on the flip-chip can be formed from solders, conductive polymers, or other materials. In applications using solder bumps, the solder bumps are reflowed to form a solder joint between the flip-chip component and the substrate. This leaves a small gap between the flip-chip and the substrate. To enhance the integrity of the joint between the die and the substrate, an underfill material is introduced into the gap. The underfill material bears some of the stress placed on the components and protects the components from moisture, chemicals, and other contaminants. The underfill material can include filler particles to increase the rigidity of the material and modify the coefficient of thermal expansion of the material.
Electronic products require packaged microelectronic devices to have an extremely high density of components in a very limited space. For example, the space available for memory devices, processors, displays, and other microelectronic components is quite limited in cell phones, PDAs, portable computers, and many other products. As such, there is a strong drive to reduce the surface area or “footprint” of a microelectronic device on a printed circuit board. Reducing the size of a microelectronic device is difficult because high performance microelectronic dies generally have more bond-pads, which result in larger ball-grid arrays and thus larger footprints. One technique used to increase the density of microelectronic dies within a given footprint is to stack one microelectronic die on top of another. For example, FIG. 1A schematically illustrates a conventional microelectronic device 4 including a first microelectronic die 10a, a second microelectronic die 10b stacked on top of the first die 10a, an interposer substrate 60 carrying the first and second dies 10a-b, a plurality of first solder bumps 20a between the first die 10a and the substrate 60, and a plurality of second solder bumps 20b (only one shown) between the first and second dies 10a-b. FIG. 1B schematically illustrates the microelectronic device 4 after reflowing the first and second solder bumps 20a-b to mechanically and electrically connect the first die 10a to the substrate 60 and the second die 10b to the first die 10a, respectively.
One drawback of the conventional microelectronic device 4 illustrated in FIGS. 1A and 1B is that during reflow the weight of the dies 10a-b may cause the heated solder bumps 20a-b to collapse such that the dies 10a-b move toward the substrate 60 in a direction X. The collapse of the solder bumps 20a-b and associated movement of the dies 10a-b can cause several problems. First, the solder from the bumps 20a-b may spread too far such that the solder from one bump 20a-b contacts the solder from an adjacent bump 20a-b and creates an electrical short in the device 4. Second, the downward movement of the dies 10a-b may leave an insufficient gap Y between the first die 10a and the substrate 60 and/or between the first and second dies 10a-b. If the gap Y between the components is too small, it is difficult to wick underfill material into the gap Y. Third, the downward movement of the dies 10a-b creates variances in the height of different devices 4, which can cause problems with molding, testing, and other post-reflow processes that require known device heights. Fourth, when the solder bumps 20b are positioned along only a central portion of the die 10b (e.g., memory dies), the second die 10b may tilt after reflow. Die tilt can also cause problems with molding, testing, and other post-reflow processes. For example, if the second die 10b is not parallel to the first die 10a, the “high side” of the second die 10b may be exposed after encapsulation. Accordingly, there is a need to improve the process of packaging dies in microelectronic devices.